Getting Started

Calyx is an intermediate language and infrastructure for building compilers that generate custom hardware accelerators. These instructions will help you set up the Calyx compiler and associated tools. By the end, you should be able to compile and simulate hardware designs generated by Calyx.

Compiler Installation

Install Rust (it should automatically install cargo).

Clone the repository:

git clone

Then build the compiler:

cargo build

You can invoke the compiler in one of two ways:

cargo run -- --help # Rebuilds the compiler if the sources changed
./target/debug/futil --help # Default debug build of the compiler

Running Core Tests

The core test suites tests the Calyx compiler passes. Install the following tools for running the core tests:

  1. runt hosts our testing infrastructure. Install with: cargo install runt
  2. jq is a command-line JSON processor:
    • Ubuntu: sudo apt install jq
    • Mac: brew install jq
    • Other platforms: JQ installation

Build the compiler:

cargo build

Then run the core tests with:

runt -i core

If everything has been installed correctly, this should not produce any failing tests.

Installing the Command-Line Driver

The Calyx driver wraps the various compiler frontends and backends to simplify running Calyx programs.

Install Flit:

pip3 install flit

Install fud (from the root of the repository):

flit -f fud/pyproject.toml install -s --deps production

Configure fud:

fud config global.futil_directory <full path to Calyx repository>

Check the fud configuration:

fud check

fud will report certain tools are not available. This is expected.


There are three ways to run Calyx programs: Verilator, Icarus Verilog, and Calyx's native interpreter. You'll want to set up at least one of these options so you can try out your code.

Icarus is an easy way to get started on most platforms. On a Mac, you can install Icarus Verilog with Homebrew by typing brew install icarus-verilog. On Ubuntu, install from source. Then install the relevant fud support by running:

fud register icarus-verilog -p fud/icarus/

Type fud check to make sure the new stage is working. (Some missing tools are expected; just pay attention to the report for stages.icarus-verilog.exec.)

You can instead consider setting up Verilator for faster long-running simulations or using the interpreter to avoid RTL simulation altogether.

Running a Hardware Design

We're all set to run a Calyx hardware design now. Run the following command:

fud e examples/tutorial/language-tutorial-iterate.futil \
  -s examples/tutorial/data.json \
  --to dat --through icarus-verilog -v

(Change the last bit to --through verilog to use Verilator instead.)

This command will compile examples/tutorial/language-tutorial-iterate.futil to Verilog using the Calyx compiler, simulate the design using the data in examples/tutorial/data.json, and generate a JSON representation of the final memory state.

Congratulations! You've simulated your first hardware design with Calyx.

Where to go next?