Calyx is an intermediate language and infrastructure for building compilers that generate custom hardware accelerators. These instructions will help you set up the Calyx compiler and associated tools. By the end, you should be able to compile and simulate hardware designs generated by Calyx.
Install Rust (it should automatically install
Clone the repository:
git clone https://github.com/cucapra/calyx.git
Then build the compiler:
You can invoke the compiler in one of two ways:
cargo run -- --help # Rebuilds the compiler if the sources changed ./target/debug/futil --help # Default debug build of the compiler
The core test suites tests the Calyx compiler passes. Install the following tools for running the core tests:
- runt hosts our testing infrastructure. Install with:
cargo install runt
- jq is a command-line JSON processor:
sudo apt install jq
brew install jq
- Other platforms: JQ installation
Build the compiler:
Then run the core tests with:
runt -i core
If everything has been installed correctly, this should not produce any failing tests.
The Calyx driver wraps the various compiler frontends and backends to simplify running Calyx programs.
pip3 install flit
fud (from the root of the repository):
flit -f fud/pyproject.toml install -s --deps production
fud config global.futil_directory <full path to Calyx repository>
fud will report certain tools are not available. This is expected.
Icarus is an easy way to get started on most platforms.
On a Mac, you can install Icarus Verilog with Homebrew by typing
brew install icarus-verilog.
On Ubuntu, install from source.
Then install the relevant fud support by running:
fud register icarus-verilog -p fud/icarus/icarus.py
fud check to make sure the new stage is working.
(Some missing tools are expected; just pay attention to the report for
We're all set to run a Calyx hardware design now. Run the following command:
fud e examples/tutorial/language-tutorial-iterate.futil \ -s verilog.data examples/tutorial/data.json \ --to dat --through icarus-verilog -v
(Change the last bit to
--through verilog to use Verilator instead.)
This command will compile
examples/tutorial/language-tutorial-iterate.futil to Verilog
using the Calyx compiler, simulate the design using the data in
examples/tutorial/data.json, and generate a JSON representation of the
final memory state.
Congratulations! You've simulated your first hardware design with Calyx.