Module passes

Passes for the Calyx compiler.

Re-exports

• pub use math_utilities::get_bit_width_from;

Modules

• math_utilities

Structs

• AddGuard
• Canonicalize
  Perform serval canonicalizations on the program.
• CellShare
  Given a LiveRangeAnalysis that specifies the “share” and “state_share” cells alive at each group, minimizes the cells used for each component.
• ClkInsertion
  Adds assignments from a components clk port to every component that contains an input clk port.
• CollapseControl
  Collapses and de-nests control constructs.
• CombProp
  Propagate unconditional reads and writes from wires.
• CompileInvoke
  Compiles ir::Invoke statements into an ir::Enable that runs the invoked component.
• CompileRepeat
  Compiles ir::Invoke statements into an ir::Enable that runs the invoked component.
• CompileStatic
  Compiles Static Islands
• ComponentInliner
  Inlines all sub-components marked with the @inline attribute. Cannot inline components when they:
• ConstantPortProp
  Replaces ports with constants when we can infer the value of the port.
• DataPathInfer
  Infers @control and @data annotations for cells. A cell marked with @data can have 'x assignments to its @data ports which enables downstream optimizations.
• DeadAssignmentRemoval
  Removes unused assigns from groups. Analyzes the writes to combinational cells in groups In order for a combinational cell to be considered “used”, it must:
• DeadCellRemoval
  Removes unused cells from components.
• DeadGroupRemoval
  Removes unused groups and combinational groups from components. A group is considered in use when it shows up in an ir::Enable. A combinational group is considered in use when it is a part of an ir::If or ir::While or ir::Invoke.
• DefaultAssigns
  Adds default assignments to all non-@data ports of an instance.
• DumpResults
  Results generated from the process of dumping out ports.
• Externalize
  Externalize input/output ports for cells marked with the @external(1) attribute. The ports of these cells are exposed through the ports of the parent component.
• GoInsertion
  Add the group’s go signal into the guards of all non-hole assignments of this group.
• GroupToInvoke
  Transform groups that are structurally invoking components into equivalent ir::Invoke statements.
• GroupToSeq
  Transforms a group into a seq of 2 smaller groups, if possible. Currently, in order for a group to be transformed must
• InferShare
  This pass checks if components are (state) shareable. Here is the process it goes through: if a component uses any ref cells, or non-shareable cells then it is automatically not shareable. Otherwise, check if each read of a stateful cell is guaranteed to be dominated by a write to the same cell– we check this by building a domination map. If so, component is state shareable.
• LowerGuards
  Lowers guards into a purely structural representation. After this pass, all guards are guaranteed to be either ir::Guard::True or ir::Guard::Port.
• MergeAssign
  Merge assignments of the form with the same (dst_port, src_port) pairs.
• Papercut
  Pass to check for common errors such as missing assignments to done holes of groups.
• ProfilerInstrumentation
  Adds probe wires to each group (includes static groups and comb groups) to detect when a group is active. Used by the profiler.
• RemoveIds
  Removes NODE_ID, BEGIN_ID, and END_ID from each control statement
• ResetInsertion
  Adds assignments from a components reset port to every component that contains an input reset port.
• SimplifyStaticGuards
  Simplifies Static Guards In particular if g = g1 & g2 & …gn, then it takes all of the g_i’s that are “static timing intervals”, e.g., %[2:3], and combines them into one timing interval. For example: (port.out | !port1.out) & (port2.out == port3.out) & %[2:8] & %[5:10] ? becomes (port.out | !port1.out) & (port2.out == port3.out) & %[5:8] ? by “combining” %[2:8] & %[5:10]
• SimplifyWithControl
  Transforms combinational groups into normal groups by registering the values read from the ports of cells used within the combinational group.
• StaticFSMOpts
  Adds assignments from a components clk port to every component that contains an input clk port.
• StaticInference
  Infer @promotable annotation for groups and control. Inference occurs whenever possible.
• StaticInliner
• StaticPromotion
  Promote control to static when (conservatively) possible, using @promote_static annotations from infer_static.
• SynthesisPapercut
  Pass to check common synthesis issues.
• TopDownCompileControl
  Core lowering pass. Compiles away the control programs in components into purely structural code using an finite-state machine (FSM).
• UnrollBounded
  Fully unroll all while loops with a given @bound.
• WellFormed
  Pass to check if the program is well-formed.
• WireInliner
  Alternate hole inliner that removes groups and group holes by instantiating wires that hold the value for each signal.
• WrapMain
  If the top-level component is not named main, adds a new main component and makes it the top-level component. This is useful because a lot of our tools rely on the name main being the design under test (DUT).