Enum Control

pub enum Control {
    Seq {
        stmts: Vec<Control>,
        attributes: Attributes,
    },
    Par {
        stmts: Vec<Control>,
        attributes: Attributes,
    },
    If {
        port: Port,
        cond: Option<Id>,
        tbranch: Box<Control>,
        fbranch: Box<Control>,
        attributes: Attributes,
    },
    While {
        port: Port,
        cond: Option<Id>,
        body: Box<Control>,
        attributes: Attributes,
    },
    Repeat {
        num_repeats: u64,
        body: Box<Control>,
        attributes: Attributes,
    },
    Enable {
        comp: Id,
        attributes: Attributes,
    },
    Invoke {
        comp: Id,
        inputs: Vec<(Id, Atom)>,
        outputs: Vec<(Id, Atom)>,
        attributes: Attributes,
        comb_group: Option<Id>,
        ref_cells: Vec<(Id, Id)>,
    },
    StaticInvoke {
        comp: Id,
        inputs: Vec<(Id, Atom)>,
        outputs: Vec<(Id, Atom)>,
        attributes: Attributes,
        ref_cells: Vec<(Id, Id)>,
        comb_group: Option<Id>,
        latency: Option<NonZeroU64>,
    },
    Empty {
        attributes: Attributes,
    },
    StaticSeq {
        stmts: Vec<Control>,
        attributes: Attributes,
        latency: Option<NonZeroU64>,
    },
    StaticPar {
        stmts: Vec<Control>,
        attributes: Attributes,
        latency: Option<NonZeroU64>,
    },
    StaticIf {
        port: Port,
        tbranch: Box<Control>,
        fbranch: Box<Control>,
        attributes: Attributes,
        latency: Option<NonZeroU64>,
    },
    StaticRepeat {
        num_repeats: u64,
        body: Box<Control>,
        attributes: Attributes,
    },
}

Control AST nodes. Since enables and static enables are indistinguishable to the AST, there is single Control Enum for both Static and Dynamic Control

Variants

Seq

Represents sequential composition of control statements.

Fields

stmts: Vec<Control>

List of Control statements to run in sequence.

attributes: Attributes

Attributes

Par

Represents parallel composition of control statements.

Fields

stmts: Vec<Control>

List of Control statements to run in sequence.

attributes: Attributes

Attributes

If

Standard imperative if statement

Fields

port: Port

Port that connects the conditional check.

cond: Option<Id>

Modules that need to be enabled to send signal on port.

tbranch: Box<Control>

Control for the true branch.

fbranch: Box<Control>

Control for the true branch.

attributes: Attributes

Attributes

While

Standard imperative while statement

Fields

port: Port

Port that connects the conditional check.

cond: Option<Id>

Modules that need to be enabled to send signal on port.

body: Box<Control>

Control for the loop body.

attributes: Attributes

Attributes

Repeat

Static Repeat (essentially a bounded while loop w/o a condition)

Fields

num_repeats: u64

Control for the true branch.

body: Box<Control>

Control for the true branch.

attributes: Attributes

Attributes

Enable

Runs the control for a list of subcomponents.

Fields

comp: Id

Group to be enabled

attributes: Attributes

Attributes

Invoke

Invoke component with input/output assignments.

Fields

comp: Id

Name of the component to be invoked.

inputs: Vec<(Id, Atom)>

Input assignments

outputs: Vec<(Id, Atom)>

Output assignments

attributes: Attributes

Attributes

comb_group: Option<Id>

Combinational group that may execute with this invoke.

ref_cells: Vec<(Id, Id)>

External cells that may execute with this invoke.

StaticInvoke

Invoke component with input/output assignments.

Fields

comp: Id

Name of the component to be invoked.

inputs: Vec<(Id, Atom)>

Input assignments

outputs: Vec<(Id, Atom)>

Output assignments

attributes: Attributes

Attributes

ref_cells: Vec<(Id, Id)>

External cells that may execute with this invoke.

comb_group: Option<Id>

Combinational group that may execute with this invoke.

latency: Option<NonZeroU64>

(optional) latency. Latency can be inferred if not given.

Empty

Control statement that does nothing.

Fields

attributes: Attributes

Attributes

StaticSeq

Represents sequential composition of static control statements.

Fields

stmts: Vec<Control>

List of Control statements to run in sequence. If not all of these stmts are static, we should error out

attributes: Attributes

Attributes

latency: Option<NonZeroU64>

Optional latency for the seq

StaticPar

Represents parallel composition of static control statements.

Fields

stmts: Vec<Control>

List of Control statements to run in sequence. If not all of these stmts are static, we should error out

attributes: Attributes

Attributes

latency: Option<NonZeroU64>

Optional latency for the par

StaticIf

Static if statement.

Fields

port: Port

Port that connects the conditional check.

tbranch: Box<Control>

Control for the true branch.

fbranch: Box<Control>

Control for the true branch.

attributes: Attributes

Attributes

latency: Option<NonZeroU64>

Optional latency; should be the longer of the two branches

StaticRepeat

Static Repeat (essentially a bounded while loop w/o a condition)

Fields

num_repeats: u64

Control for the true branch.

body: Box<Control>

Control for the true branch.

attributes: Attributes

Attributes

Implementations

impl Control

pub fn empty() -> Control

pub fn get_attributes(&self) -> &Attributes

Trait Implementations

impl Debug for Control

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.