Module calyx::passes

Passes for the Calyx compiler.

Structs

Canonicalize

Perform serval canonicalizations on the program.

CellShare

Given a LiveRangeAnalysis that specifies the “share” and “state_share” cells alive at each group, minimizes the cells used for each component.

ClkInsertion

Adds assignments from a components clk port to every component that contains an input clk port.

CollapseControl

Collapses and de-nests control constructs.

CombProp

Propagate unconditional reads and writes from wires.

CompileEmpty

Compiles away all ir::Empty statements into an ir::Enable.

CompileInvoke

Compiles ir::Invoke statements into an ir::Enable that runs the invoked component.

CompileRef

Remove all the cells marked with the ‘ref’ keyword

Inline all the ports of the ref cells to the component signature

Remove all the ref cell mappings from the invoke statement

Inline all the mappings of ports to the invoke signature

CompileSync

loop through all control statements under “par” block to find # barriers needed and # members of each barrier

add all cells and groups needed

loop through all control statements, find the statements with @sync attribute and replace them with seq { ; incr_barrier_0_; write_barrier_0_; wait_; restore_; } or seq { ; incr_barrier__; write_barrier__; wait_; wait_restore_; }

ComponentInliner

Inlines all sub-components marked with the @inline attribute. Cannot inline components when they:

ComponentInterface

Wires up the go and done holes for Calyx programs with a single enable to the component go and done ports.

DeadCellRemoval

Removes unused cells from components.

DeadGroupRemoval

Removes unused groups and combinational groups from components. A group is considered in use when it shows up in an ir::Enable. A combinational group is considered in use when it is a part of an ir::If or ir::While or ir::Invoke.

Externalize

Externalize input/output ports for cells marked with the @external(1) attribute. The ports of these cells are exposed through the ports of the parent component.

GoInsertion

Add the group’s go signal into the guards of all non-hole assignments of this group.

GroupToInvoke

Transform groups that are structurally invoking components into equivalent ir::Invoke statements.

GroupToSeq

Transforms a group into a seq of 2 smaller groups, if possible. Currently, in order for a group to be transformed must

HoleInliner

Removes all groups and inlines reads and writes from holes.

InferShare

This pass checks if components are (state) shareable. Here is the process it goes through: if a component uses any ref cells, or non-shareable cells then it is automatically not shareable. Otherwise, check if each read of a stateful cell is guaranteed to be dominated by a write to the same cell– we check this by building a domination map. If so, component is state shareable.

InferStaticTiming

Infer “static” annotation for groups and add “@static” annotation when (conservatively) possible.

LowerGuards

Lowers guards into a purely structural representation. After this pass, all guards are guaranteed to be either ir::Guard::True or ir::Guard::Port.

MergeAssign

Merge assignments of the form with the same (dst_port, src_port) pairs.

MergeStaticPar

under a par control block, if multiple groups have the same static attribute, then merge them together.

Papercut

Pass to check for common errors such as missing assignments to done holes of groups.

ParToSeq

Transforms all par into seq. Uses analysis::ControlOrder to get a sequentialization of par such that the program still computes the same value. When there is no such sequentialization, errors out.

RegisterUnsharing

Unsharing registers reduces the amount of multiplexers used in the final design, trading them off for more memory.

RemoveCombGroups

Transforms combinational groups, which have a constant done condition, into proper groups by registering the values read from the ports of cells used within the combinational group.

RemoveIds

Removes NODE_ID, BEGIN_ID, and END_ID from each control statement

ResetInsertion

Adds assignments from a components reset port to every component that contains an input reset port.

SimplifyGuards

Simplify guards using BDDs and other heuristic tricks. Not used in the default compilation pipeline.

StaticParConv

Transforms a par of seq blocks into a seq of par blocks. It will sometimes only apply this transformation to a subset of seq blocks in the par block. Regardless, this transformation should never increase the number of cycles the par block takes to execute.

SynthesisPapercut

Pass to check common synthesis issues.

TopDownCompileControl

Core lowering pass. Compiles away the control programs in components into purely structural code using an finite-state machine (FSM).

TopDownStaticTiming

Lowering pass that generates latency-sensitive FSMs when control sub-programs have @static annotations. The pass works opportunisitically and attempts to compile all nested static control programs nested within the overall program, replacing them with groups that implement the correct transitions.

UnrollBounded

Fully unroll all while loops with a given @bound.

WellFormed

Pass to check if the program is well-formed.

WireInliner

Alternate hole inliner that removes groups and group holes by instantiating wires that hold the value for each signal.